This invention relates to a high-speed flip-flop circuit possessing functions substantially equivalent to those of a delay flip-flop.
A delay flip-flop (hereinafter referred to as a D-FF) is in general a circuit that takes in data in synchronization with a clock signal and outputs it at a certain time. At high clock frequencies, this type of D-FF is liable to malfunction in taking in the data. Various flip-flop circuits (hereinafter referred to as FF circuits) suitable for high-speed operation have therefore been proposed.
A prior-art FF circuit of this type has been described in the article "5-Gbit/s Si Integrated Regenerative Demultiplexer and Decision Circuit" by Detlef Clawin, Ulrich Langmann, and Hans-Ulrich Schreiber, published on pages 385 to 389 of the (American) IEEE Journal of Solid-State Circuits, Vol. SC-22, No. 3, in Jun. 1987. A description thereof will be given with reference to the drawings.
FIG. 1 is a block diagram showing an example of the configuration of a prior-art FF circuit.
This FF circuit comprises a pair of master-slave flip-flops (hereinafter referred to as MS-FFs) 1 and 2 for latching data Di and the inverted data Di in synchronization with a clock signal CL and its inverted clock signal CL, and a selector 3 for selecting the outputs of the MS-FFs 1 and 2 responsive to the clock signal CL and the inverted clock signal CL and producing them in the form of data Do and the inverted data Do.
The MS-FF 1 is a circuit that latches the data Di and the inverted data Di on the rise of the clock signal CL and outputs them on the fall of the clock signal CL, and has an input terminal D1 for input of the data Di, an inverted input terminal D1 for input of the inverted data Di, a clock input terminal C1 for input of the clock signal CL, an inverted clock input terminal C1 for input of the inverted clock signal, an output terminal Q1, and an inverted output terminal Q1. The MS-FF 2 is a circuit that latches the data Di and the inverted data Di on the rise of inverted clock signal CL and outputs them on the fall of the inverted clock signal CL, and has an input terminal D2 for input of the data Di, an inverted input terminal D2 for input of the inverted data Di, a clock input terminal C2 for input of the inverted clock signal CL, an inverted clock input terminal C2 for input of the clock signal CL, an output terminal Q2, and an inverted output terminal Q2. The selector 3 has an input terminal I1 connected to the output terminal Q1, an inverted input terminal I1 connected to the inverted output terminal Q1, an input terminal I2 connected to the output terminal Q2, an inverted input terminal I2 connected to the inverted output terminal Q2, a control terminal CS for input of the clock signal CL, an inverted control terminal CS for input of the inverted clock signal CL, an output terminal O for output of the data Do, and an inverted output terminal O for output of the inverted data Do. When the logic level of the control terminal CS is high (hereinafter denoted "H") and the logic level of the inverted control terminal CS is low (hereinafter denoted "L"), the selector 3 produces the logic level of the input terminal I1 at the output terminal O, and produces the logic level of the inverted input terminal I1 at the inverted output terminal O; when the control terminal CS is "L" and the inverted control terminal CS is "H," it produces the logic level of the terminal I2 at the output terminal O and the logic level of the inverted input terminal I2 at the inverted output terminal O .
FIGS. 2a-2j are timing charts for FIG. 1, with times t0 to t4 indicated on the horizontal axis. The operation of FIG. 1 will be explained with reference to this chart.
At time t0, the clock signal CL is "H," the inverted clock signal is "L," the data Di is "L,", and the inverted data Di is "H," so the output terminal Q1 of the MS-FF 1 is held at "L," the inverted output terminal Q1 is held at "H," the output terminal Q2 of the MS-FF 2 goes to "L," and the inverted output terminal Q2 goes to "H," making the data Do at the output terminal O of the selector 3 "L" and the inverted data Do at the inverted output terminal O H.
At time t1, when the clock signal CL goes to "L" and the inverted clock signal CL goes to "H," since the data Di is "H" and the inverted data Di is "L," the output terminal Q1 of the MS-FF 1 rises to "H" and the inverted output terminal Q1 falls to "L." The output terminals Q2 and Q2 are not changed.
At time t2, when the clock signal CL goes to "H" and the inverted clock signal CL goes to "L," since the data Di is "L" and the inverted data Di is "H," the output terminal Q2 of the MS-FF 2 is "L" and the inverted output terminal Q2 is "H," the output terminal Q1 of the MS-FF 1 remains "H" and the inverted output terminal Q1 remains "L." The data Do at the output terminal O of the selector 3 is therefore "H," and the inverted data Do at the inverted output terminal O is "L."
At time t3, when the clock signal CL goes to "L" and the inverted clock signal CL goes to "H," since the data Di is "H" and the inverted data Di is "L," the output terminal Q1 of the MS-FF 1 is "H" and the inverted output terminal Q1 is "L," the output terminal Q2 of the MS-FF 2 remains "L" and the inverted output terminal Q2 remains "H," the data Do goes to "L," and the inverted data Do goes to "H."
At time t4, when the clock signal CL goes to "H" and the inverted clock signal CL goes to "L," since the data Di is "H" and the inverted data Di is "L," the output terminal Q1 of the MS-FF 1 remains "H" and the inverted output terminal Q1 remains "L," the output terminal Q2 of the MS-FF 2 goes to "H" and the inverted output terminal Q2 goes to "L," and the data Do goes to "H" while the inverted data Do goes to "L."
The FF circuit in FIG. 1 thus operates as a D-FF by outputting the logic levels of the data Di and the inverted data Di when the clock signal CL and the inverted clock signal CL change as the data Do and inverted data Do at the next change of the clock signal CL and the inverted clock signal CL. When the clock signal CL is "H" and the inverted clock signal CL is "L," the output signals of the MS-FF 1 are output by the selector 3, while when the clock signal CL is "L" and the inverted clock signal CL is "H," the output signals of the MS-FF 2 are output by the selector 3, so stable, high-speed operation is possible even at high frequencies of the clock signal CL.
The reason that the FF circuit in FIG. 1 is capable of high-speed operation can be stated as follows. The FF circuit in FIG. 1 is constructed so that the MS-FF 1 and the MS-FF 2 operate at only half the clock frequency at which they would operate if used as stand-alone D-FFs. The FF circuit in FIG. 1 can therefore operate at a bit rate equal to twice the limiting clock frequency of a stand-alone D-FF.
A problem with the FF circuit described above is that, since it employs two MS-FFs 1 and 2 and a selector 3, if these comprise NOR gates, for example, eighteen to twenty-two NOR gates are required; the large number of elements required and the complex circuit structure present an obstacle to high levels of circuit integration, and consume more power than the usual D-FF. A further problem is that the output is delayed by one bit as compared with the usual D-FF, which restricts the applicability of the circuit.